1. Field of the Invention
The invention relates to information processing systems, and in particular to apparatus and methods for increasing an effective bandwidth of a system bus for commanding a co-processor.
2. Background of the Invention
A co-processor, as the word is used in this patent application, is an element in an information processing system. The co-processor is commanded by a central information processor (hereafter "processor") of the system to perform a portion of an information processing task. Thus the task is shared between the processor and a co-processor.
The purpose of a co-processor in such a system is to permit the system to perform a more complex computational task than would be possible without the existence of the co-processor. The co-processor increases the total computational power of the whole information processing system. The phrase "computational task," as used here, means any and everything an information processing system is called upon to do.
A common example of such an arrangement is the graphics accelerator used to increase the responsiveness of a graphics display, which task would--if attempted solely by the processor--be difficult or impossible to perform at an equivalent level of responsiveness.
In deciding when the use of a co-processor is feasible, the system architect defines a particular computational task, decides how much of the task can realistically be carried out by the processor, and identifies a major portion of the task that will be handled by an, independent co-processor.
In such a division of responsibility, it is necessary for the processor to tell the co-processor what to do, and to provide the co-processor with information needed by the co-processor to carry out its part of the overall task. The processor tells the co-processor what to do by sending it a command, and by sending the needed information as a set of command parameters. The command and command parameters are usually referred to as a command block.
A command block is typically transferred between the processor and the co-processor via a system bus using a sequence of WRITE commands. It is typical for each WRITE command to have an ADDRESS phase and a DATA phase. During the ADDRESS phase, the processor sends an address to the co-processor to cause the co-processor to accept the command block, to identify the information being sent, and to specify which co-processor register receives each parameter. During the DATA phase, the processor sends the command and the various command parameters needed for that particular type of command.
In some system buses, the ADDRESS phase and the DATA phase use separate lines and occur simultaneously. In other bus systems the two phases of the WRITE command share a common set of lines and the ADDRESS phase precedes the corresponding DATA phase.
It is typical to place one or more whole parameters within the DATA phase and to use one WRITE command for transferring those parameters to a co-processor. A sequence of WRITE commands continues until the co-processor command and all its parameters have been transferred. It is also typical to pack as many of the whole parameters as will fit within the DATA phase of each WRITE command. But once a packing scheme has been determined, it is not altered for different types of co-processor commands. Thus, it is common that parameters are passed and then discarded in order to pass one of the parameters in a specific packing scheme that will be used.
It is typical also to use a portion of the ADDRESS phase of each WRITE command is identify the specific parameters being passed. The information is used by the co-processor to insure that each accepted parameter is loaded into the correct co-processor parameter register. This arrangement permits the processor to send the packed parameters in any convenient order--sometimes an advantage in existing systems.
The parameters vary in number and length depending upon the specific co-processor command being sent. At the present time, a typical DATA phase can deliver 32 bits (4 bytes) of information to the co-processor. But since only whole parameters are delivered with each WRITE command, and since the parameters vary in length, there is often inefficiency whenever all 32 bits are unable to be used. The unused bits in each WRITE command are simply wasted. So there is potential waste because all the bits cannot be used, and also because unneeded parameters may be passed.
This situation was not so much of a problem in the past when the speed of the processor and the co-processor were relatively low compared with the bandwidth of the bus. But processor speeds have increased rapidly, as have the speeds of the co-processors. System bus speeds, on the other hand, have remained relatively low in comparison with the speeds of the processors and the co-processors. The speed of the bus is referred to as its bandwidth, so a slow bus is one having a narrow or low bandwidth. The narrow bandwidth system bus has thus become a bottleneck in the task of a processor commanding a co-processor. Command blocks must be shoved through this bottleneck by a very fast processor to a very fast co-processor.
It would be desirable to permit the co-processor to perform as large a portion of the shared computational task as possible, but many tasks which the co-processor could reasonably be expected to carry out are quite small yet require the transfer of many parameters. The system bus bottleneck works against such sharing of the computational task.
What is needed is a way to effectively increase ("more fully utilize") the available bandwidth of a system bus so that the co-processor can realistically assume the burden of these many smaller tasks, freeing the processor for other system work.